Document sans titre

DTS Conference Chairs

Dr. Salem Abdennadher
Intel Corporation - USA
Prof. Slim Abdennadher
GIU - Egypt
Prof. Mohamed Masmoudi
National Engineering School of Sfax (ENIS) - Tunisia

Committees

Sponsors & Partners

News
Registration process and fees are available

IEEE DTS'22 is completely Switched to Virtual


IEEE DTS’22 Panel Discussion

Creating Robust EDA and IP Ecosystems for the Bleeding Edge

In this panel, thought leaders from leading EDA, IP and semiconductor companies will discuss how they collaborate to create robust EDA and IP ecosystems to enable the new generation of advanced processors and systems which could potentially change the semiconductor landscape. These include processors for AI-ML, 5G-6G, Cloud and Edge Computing.

Here are some among many open challenges that we would like our panelists to address:

  • What will it take to enable AI-ML, 5G-6G, Edge computing?
  • What kind of an ecosystem do we need to enable Cloud computing?
    • Private clouds, public clouds, hybrid clouds, and multi-clouds
    • Infrastructure-as-a-Service (IaaS), Platforms-as-a-Service (PaaS), and Software-as-a-Service (SaaS)
  • What kind of a Hardware Platform will work best?
    • Open/Closed/Heterogeneous? X86, ARM, RISC-V? CPUs-GPUs-AI/Graph processors?
  • Software defined Hardware: how will it work?
  • Is Architecture Aware Design Automation the answer?
  • RTL Generation, Python, Pytorch: what next?
  • How about Packaging? 3D? Chiplets?

Organizers:
Shankar Hemmady
, Director of Strategic Sourcing, Intel Foundry Services
Ram Rangarajan, Sr. Principal Engineer, Client Computing Group, Intel

Chair:

Shankar Hemmady, Director of Strategic Sourcing, Intel Foundry Services

Biography: Shankar Hemmady is Director of Strategy at Intel responsible for EDA and IP sourcing for foundry customers and Intel design teams. Over the past 30 years, Shankar has been an entrepreneur and executive at major software, EDA and semiconductor companies including Cadence, Oracle, and Synopsys. He has led product definition, marketing and delivery of software, hardware, IP and services. He has also served as an advisor and leadership coach to a few technology startups and social service organizations in USA, India and Mexico.  From 1989, Shankar has presented over a dozen papers, posters, led tutorials, panels and workshops at DAC, DVCon, DesignCon and other conferences and seminars. He also co-authored a book published by Springer: “Metric Driven Design: an Engineer’s and Executive’s Guide of First-pass Success”

Moderator:
Ed Sperling
, Editor in Chief, Semiconductor Engineering

Ed Sperling is the editor in chief of Semiconductor Engineering. He is a technology industry veteran and frequent moderator and speaker in Silicon Valley. Sperling is a former contributing editor at Forbes, where he wrote nearly 200 articles about business and technology issues affecting IT and CIOs. He was previously editor in chief of Electronic News and Electronic Business, and before that he held top editorial positions at Ziff-Davis and CMP Publications.

Panelists:

  • Rob Aitken, Fellow & Director of Technology, Arm

Rob Aitken works on design and technology issues including energy-efficient compute, hardware security, and emerging technologies. He has worked on 15+ Moore’s law nodes and has published over 100 technical papers on a wide range of topics.  He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees.

  • Bari Biswas, Sr. Vice President, Silicon Realization Group, Synopsys

Bari Biswas is Sr. Vice President of Engineering in Silicon Realization Group at Synopsys responsible for Customer Solutions and Ecosystem organization. Bari manages strategic partnerships with key foundries and IP providers and jointly enable success of entire semiconductor ecosystem.  His team delivers innovative solutions for customers doing digital designs. Prior to that for over 15 years, Bari led R&D of market leading EDA products (PrimeTime and StarRC). Bari received his MS in Computer Engineering from North Carolina State University at Raleigh and his bachelor’s degree in Electrical Engineering from Indian Institute of Technology, Kanpur.

  • Mohamed Elmalaki, Sr. Principal Engineer, Edge AI Product Architect, Intel

Mohamed Elmalaki is a Senior Principal Engineer of Intel. Mohamed has been at Intel for 10 years where he worked up and down the silicon design stack from architecture to SoC/IP execution. Mohamed executed 10 IPs now in all Intel mainstream products and 4 SoC projects all hitting top quality PRQ. Mohamed is an expert in AI accelerator architecture, working on 3 different AI accelerators during his tenure at Intel. Mohamed is attributed to driving/inventing key differentiating features into IOT products.  Mohamed is also an industry expert in Pre-Silicon Verification. Mohamed was a main contributor in the pre-si verification standard “UVM” used by 10s of thousands of engineers world-wide. Mohamed led the UVM TLM2.0 task force and contributed to resource manager, and authored the UVM User Guide. Mohamed holds a M.Sc degree in Computer Engineering from Ain Shams University, Cairo, Egypt. Mohamed has 8 patents, participated in 2 DAC invited talks, published 11 peer reviewed journal and conference papers. Outside work, Mohamed is a cub scouts den lead. In his free time Mohamed enjoys soccer, runs, hikes and spending time with his two boys.

  • Michael Jackson, Corporate Vice President, R&D, Cadence

Michael Jackson joined Cadence in 2019 and is a Corporate Vice President of R&D in the PCB and Packaging Group where he leads Cadence’s electrical and physical signoff products. He joined Synopsys in 2002 and led engineering for their synthesis, test and physical design products and later led marketing, business development and strategy for Synopsys’ Design Group. Prior to joining Synopsys, he led engineering for Avant!'s physical design and simulation product lines and he also led the design technology group in Motorola's Semiconductor Products Sector. Michael earned a BS in Electrical Engineering from the University of Arizona and a Ph.D. in Electrical Engineering and Computer Sciences from the University of California at Berkeley.

  • John Lee, Vice President & GM, Electronics and Semiconductor BU, Ansys

John Lee is GM/VP of the Semiconductor Business Unit at ANSYS.
He received his undergraduate and graduate degrees from Carnegie Mellon University. Previously he was CEO of Gear Design Solutions (acquired by ANSYS in 2015) and a co-founder of Performance Signal Integrity (founded in 1992; acquired by Avant! in 1994) which led to Star-RCXT, and Mojave Design which led to Quartz DRC (founded in 2002; acquired by Magma in 2004).  John is also active as a board member for technology and non-profit organizations.

  • Prashant Varshney, Head of Product, Silicon Vertical, Microsoft Azure