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IEEE DTS Conference Chair

Pr. Mohamed Masmoudi
National Engineering School of Sfax (ENIS) - Tunisia

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IEEE DTS’20 Workshops

Workshop 1

What’s up with Analog Defect Coverage?

Workshop Summary:
There have been a variety of analog defect models in use over the past 30 years. Some relied on mapping manufacturing defects to devices and circuits relying on process variations, block-level parametric variations, and circuit-level specification variations. One of the common limitations of these analog defect models is how theoretically valid, experimentally verifiable, and computationally efficient to support test developments and quality improvements. There have been obvious impediments to the development of a standard to address analog defect model. The process to create most of the existing used models have never been clarified, never been unified in industry, and always left as future work to be done later. IEEE P2427 WG is addressing the future now by working on a standard that defines a defect coverage accounting method based on simulation models for manufacturing defects observed within analog integrated circuits (ICs). IEEE P2427 Working Group draft standard is being produced that includes: state-of-the-art in analog defect simulation summary, an extensive set of concise definitions, and rules/recommendations for clear reporting on analog defect and fault coverage. This workshop will introduce this new proposed standard which defines a defect coverage accounting method based on simulation models for manufacturing defects observed within integrated circuits. The portion of all possible defects that are detected by manufacturing and System level tests of analog and mixed-signal circuits in practice depends on many factors: detectability, defect characteristics, detection threshold margin, measurement resolution, operating point, test patterns, ….), which this standard considers as it defines how to report coverage.

Presenter:
Full name: Salem Abdennadher
Affiliation: Intel Corporation
Email:
salem.abdennadher@intel.com

Presenter Biography:
Salem Abdennadher, Principal Engineer, Intel Corporation has 20+ years of experience in mixed-signal design and DFT. Soon after graduating with Masters from Oregon State University 1992, he joined the industry and has worked with a research lab in Tunisia, Motorola, Level One Communications and Intel. His recent publications and international patent filing in mixed signal DFT/BIST ranges from Filter BIST, On-chip Jitter BIST, to mixed signal behavioral modeling and noise extraction and prediction. Salem also has presented dozens of tutorials through TTEP at ATS, LATW, VTS, ITC. Presented multiple Workshops, publication, Special sessions presentation in International test Conference, VLSI test Symposium. European Test Symposium, Latin test Workshop

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